SURE: Securing Reconfigurable Hardware in the Era of AI

Purpose and goal:

The goal of this project was to create open-source security assessment methods and countermeasures against side-channel attacks on cryptoalgorithms implemented in Field Programmable Gate Arrays (FPGA). The project has succeeded in achieving this goal. We developed new approaches for analyzing information leakage from FPGAs and a countermeasure capable of mitigating the leakage.

A prototype demonstrating the countermeasure is built and evaluated in terms of resource efficiency and security. All related data are made open-source. Expected results and effects:

The project has delivered ten peer-reviewed research papers which describe new, AI-based methods for analyzing information leakage from FPGA implementations and a new countermeasure against side-channel attacks. The developed knowledge and tools are expected to help hardware designers develop FPGA-based products which are more resistant to secret key extraction and IP theft.

The new countermeasure can be incorporated into a product at the design stage, which contributes to a proactive vulnerability management. Approach and implementation:

The project has started on 2021-07-01 and was completed in 26 months. KTH led work packages related to the development of new security assessment methods, the design of countermeasures, and the prototype implementation. Ericsson contributed to the design of countermeasures and the security evaluation. VINNOVA´s funding enabled us to build up a strong team which carried out verification of new ideas. We identified a number of research challenges which we will address in a follow up project.