Fault-tolerant Architecture for Low-cost Scalable, Superconducting Qubits (FALSS-Q)

Purpose and goal:

This project has the primary goal of developing novel JJs and integrating those designs into qubits with the express intention of scaling the process into a viable commercial product. Within that goal, the project aims to develop the minimum viable solution which can meet client specifications and be competitive compared to qubits which are already on the market or under development by other commercial players.

Expected results and effects:

The proposed process is expected to not only alleviate design constraints, but also allow cheaper lithographic processes such as laser writing. The project aims to develop a qubit system which can be realized at low cost and wafer scale with much more reliability than current processes. As such, the proposed technology has the potential to shift the paradigm of industrial quantum computer processing.

Approach and implementation:

The project will be divided into 4 work packages. WP1 will consist of project management, namely, monitoring and controlling process work, WP2 will consist of JJ development and WP3 consists of process integration. Finally, WP4 involves dissemination and outreach to potential clients.