Experimental ferroelectric memristor-based in-memory computing platform for energy-efficient 6G

Purpose and goal:

The goal of this multidisciplinary project was to combine expertise from three distinct research fields to develop an energy-efficient in-memory computing platform. The project involved utilizing device physics to fabricate scalable memristive devices with variable conductance levels. We successfully implemented an analog interface and readout circuit to extract and process signals before transitioning them to the digital domain.

Moreover, the high-performance FPGA controlled the entire platform while executing digital processing tasks such as matrix multiplication. Expected results and effects:

In this project, we successfully utilized highly scalable ferroelectric tunnel junction (FTJ) memristive devices to implement a platform for artificial intelligence (AI) and next-generation wireless communications (6G). The in-memory computation platform developed through this project aims to significantly enhance the energy efficiency of future high-performance computing, compared to the conventional von Neumann architecture, which involves frequent data transfers between memory and the processing unit.

Approach and implementation:

The planned approach was divided into three parallel phases. First, we aimed to implement reliable FTJ memristive devices with a high production yield in the lab. Next, we extracted the necessary specifications for the interface and control circuits to design and implement the analog circuit board for the memristive array.

Then, the digital algorithms were implemented in a HDL programming language, based on speed and array size requirements. Finally, all groups synchronized their activities to achieve the project’s ultimate goal of implementing an in-memory computation platform.