6G Harmonic Oscillators in CMOS Processes

We plan to design voltage-controlled oscillators and frequency multipliers in a 22nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process, to be deployed in 6G radio stations.

We target frequency generation up to 100 GHz, as a well as the lowest phase noise ever achieved in an ultra-scaled CMOS process, in order to meet the superior spectral purity required by ultra-wide-band communications.To this aim, we will exploit a new oscillator architecture, which employs the series resonance of an inductance L and a capacitance C, rather than the traditional parallel resonance between L and C.

In this way, the oscillation amplitude is boosted in direct proportion to the quality factor of the series of L and C, and the amplitude limitations imposed by the very low power supply voltage typical of nm CMOS processes are largely overridden.

A second fundamental goal of the project is to improve the theoretical understanding of the mechanisms responsible for phase noise generation in a series-resonance oscillator, which appear to be quite distinct from those at work in transconductor-based oscillators.

Building upon already obtained partial results revealing a surprising phase noise behavior, we aim at a complete theory of phase noise in a series-resonance oscillator, with particular emphasis on the increasingly important up-conversion of 1/f noise into phase noise.