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| Funder | Vinnova |
|---|---|
| Recipient Organization | Kth, Royal Institute of Technology |
| Country | Sweden |
| Start Date | Sep 01, 2024 |
| End Date | Aug 31, 2027 |
| Duration | 1,094 days |
| Number of Grantees | 1 |
| Roles | Principal Investigator |
| Data Source | Swedish Research Council |
| Grant ID | 2024-00553_Vinnova |
Purpose and goal:
The objective is to enhance the Lego-inspired design framework called SiLago at KTH, which can deal with dynamic applications and has system-level infrastructural resources. Strikersoft, the industrial partner will develop AI/ML application to detect objects in a disaster zone at long distance using mmWave radar, and vitals at a short distance. The application will be mapped to COTS for functional verification and demonstration.
The application will also be mapped to the SiLago. The two implementations will be compared to validate 10-100X better energy efficiency of SiLago. Expected results and effects: 1. The enhanced SíLago platform will have broader applicability
2. Validating 10X to 100X better efficiency will increase the credibility of SiLago as a competitive alternative to COTS for implementing challenging AI/ML applications.
3. Strikersoft´s demo of using mmWave radar in detecting objects and vitals (from close distance) would contribute to improved search and rescue operations in the future.
4. KTH and Strikersoft, with increased competence in energy-efficient implementation of challenging AI/ML applications, would contribute to sustainable progress in Sweden. Approach and implementation: Strikersoft will develop requirements specifications as part of WP1.
Strikersoft, in WP6, will develop an AI/ML solution for its mmWave-based search and rescue operation use case. Strikersoft will also secure training and validation data. Strikersoft will map the use case to FPGA.
KTH, in WP4, will a) enhance the SiLago platform for dealing with dynamic applications and have system-level infrastructure, b) map the Strikersoft use case to the enhanced SiLago and benchmark against the FPGA implementation to validate its claim of 10X to 100X better energy efficiency.
Kth, Royal Institute of Technology
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