IntelliCache: Intelligent Cache Systems

Purpose and goal: The IntelliCache project will build the Cache-MX IP block on FPGA that will yield a doubling of cache capacity and commit at least 1 server customer. Expected results and effects:

The project targets to demonstrate an increase in the capacity of cache design through inline real-time data compression. The demonstration will happen on a FPGA platform prototype. Increasing the cache capacity has paramount effects in the performance and energy consumption of processor systems given the increasing demands for more memory due to the emerging applications. A doubling of the cache capacity

would improve performance by roughly 15% and reduce the energy consumption by about 15% yielding an improvement in performance/watt by 35% (i.e., 1.15/0.85 = 1.35). Approach and implementation:

The project coordinator is ZeroPoint. There are 2 participating parties: ZeroPoint & Chalmers. The activities are organized in 3 workpackages.

WP1 and WP2 have started. WP1 is responsible for adapting the Cache IP to meet the requirements and specifications for the target compressed cache, whilst WP2 is responsible for implementing the Cache-MX IP and the interface. WP3 focuses on the demonstration platform specification and implementation of it that will further integrate the results of WP1 and WP2. The project has started by following the Gantt chart, as disclosed in the proposal.