CAREER: An Ultra-low Power Analog Computing Hardware Design Framework for Machine Learning Inference in Edge Biomedical Devices

Wearable and implantable biomedical devices have advanced healthcare through the development of continuous sensing, monitoring, and timely medical interventions. Their growth has been enabled by innovation in technologies and low-power system design. We are also seeing a rapid adoption of machine-learning (ML) techniques in healthcare applications.

However, a significant technological gap exists when it comes to adopting ML techniques for wearable and implantable biomedical hardware because of the relatively high power consumption and chip area requirements associated with ML solutions. This project aims to develop ML-based hardware solutions for wearable and implantable biomedical devices. To realize power and device size goals, analog computing will be used to develop the ML hardware platform.

The proposed analog computing platform will be used to develop ultra-low power ML hardware for detecting arrythmia and obstructive sleep apnea. The research outcomes from this project will be integrated into education to develop new graduate and undergraduate courses on ML and power management. Undergraduate and high-school students will participate in the research through the Young Scholar Program (YSP) and REU outreach activities.

The project will provide a platform for training graduate and undergraduate students on biomedical devices, circuit and chip design, and ML hardware design. Outreach activities will involve K-12 students.

This project is centered around the realization of ultra-low power (ULP) machine learning (ML) system-on-chip (SoC) hardware with inference capability for wearable and implantable biomedical applications. Power consumption and device size requirements make it challenging to integrate ML solutions in mobile health devices. To realize the power consumption and device size minimization goals, robust sub-threshold analog computing circuits will be developed while overcoming variability issues previously associated with analog computing.

A new analog system modeling and simulation tool will be created to associate power consumption, noise, linearity, and other performance goals of analog circuits with the classification accuracy of a given ML network to realize area, power, and performance optimized ML hardware. The analog computing hardware framework will be developed with a new constant transconductance-based sub-threshold design to realize high energy efficiency and robustness goals.

The approach will also support multi-layer analog computing designs without the need for interfacing amplifiers or converters for signal conditioning. The resulting modeling and simulation tool will associate circuit design goals with ML classification accuracy. It will further help in reducing power and area to develop tailored analog circuits for ML networks with specific power and performance goals while maintaining the required classification accuracies.

To exemplify the design approach, the analog system modeling tool and robust analog computing circuits will be utilized to develop an ultra-low power analog SoC to demonstrate ML applications for ECG and pulse oximetry, with the goal to show up to 50-times reduction in power consumption while maintaining a high classification accuracy.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.