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| Funder | National Science Foundation (US) |
|---|---|
| Recipient Organization | University of California-Berkeley |
| Country | United States |
| Start Date | Jun 01, 2023 |
| End Date | May 31, 2028 |
| Duration | 1,826 days |
| Number of Grantees | 1 |
| Roles | Principal Investigator |
| Data Source | National Science Foundation (US) |
| Grant ID | 2238346 |
In the era of diminishing returns from technology scaling, hardware acceleration is one of the most promising approaches to deliver improved performance and energy efficiency for future computing platforms. However, state-of-the-art accelerator research has largely focused on individual accelerator development for a handful of algorithms, without a systematic understanding of how to holistically generate many accelerators at scale while improving the overall execution quality.
To address the limitation, the goal of this project is to develop a quality-driven accelerator design flow that enables the holistic simulation, design, and integration of domain-specific accelerators at scale for end-to-end applications. It will especially benefit emerging real-time applications, such as robotics and self-driving vehicles, which feature a range of computationally demanding kernels.
In addition, the integrated education activities will broaden participation in computing at all levels with outreach activities to engage K-12, undergraduate, and graduate students in exciting opportunities in the hardware industry.
This project will advance the state of knowledge in computer architecture on how to effectively generate domain-specific systems at scale to achieve end-to-end acceleration. Toward this goal, the project investigates the following three synergistic research thrusts: 1) design a hardware-software co-simulation infrastructure to quantitatively evaluate the end-to-end performance of closed-loop autonomous systems; 2) develop a holistic design-space exploration framework to efficiently construct, represent, and navigate the complex design space of entire systems-on-chip; and 3) build an adaptive contention management system through hardware-software co-design to dynamically partition shared resources between accelerators.
The methodology and framework the project develops will be open-sourced and enable accelerator integration at a greater scale than what can be done today, fundamentally advancing the field of heterogeneous system design.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
University of California-Berkeley
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