ERI: Towards Ubiquitous Circuit Robustness Through Graph Neural Network

With the rising cost associated with chip manufacturing, domestic chip companies have chosen to delegate costly fabrication processes to foreign foundries. While these third-party fabrication services can significantly alleviate the design burden and reduce the expenses associated with maintaining expensive foundries, they also introduce security risks.

Malicious actors can potentially exploit this situation, leading to the manipulation and degradation of hardware components at any point within the entire chip supply chain. For the past decade, logic-locking research, which introduces additional key gates or states in both combinational and sequential circuits, offers potential opportunities for integrating hardware security measures into the commercial chip design process.

While previous work on logic-locking has explored different aspects of developing countermeasures, the absence of a systematic analysis and associated overhead associated with locking methods have had a notable impact on the practicality of employing logic-locking techniques. Taking these observations into consideration, this project seeks to establish a new infrastructure that heavily relies on graph neural networks to investigate the characteristics of different logic locking techniques.

This method will streamline the advancement of logic-locking techniques, thereby enhancing their feasibility within contemporary integrated circuit (IC) design workflows. This project can ultimately shift logic-locking from in-lab research to a recognized industry standard for safeguarding intellectual property. Furthermore, this project aims to disseminate insights and breakthroughs through the publication of scholarly articles, as well as the release of open-source software, demonstration resources, and datasets to the wider community.

This project will also have significant impact on education by incorporating research findings into university curriculum and providing unique learning opportunities for students, including those from underrepresented groups. Through these efforts, the project will enhance our comprehension and capabilities in hardware security and will also cultivate a new generation of students and engineers equipped with the necessary knowledge and tools to address future challenges in this rapidly evolving field.

The goal of this project is to advance the field of hardware security techniques and foundational elements by harnessing advanced graph neural networks. To achieve this goal, this project promotes the development of an infrastructure that utilizes graph neural networks to learn features of various locking techniques, build models based on logic locking principles, generate novel locking methods through transfer learning, and deploy generated locking strategies to hardware implementations.

The project will be structured around three tightly intertwined research thrusts: 1) developing graph neural network models centered around sequential logic locking methods; 2) advancing transfer learning methodologies applied to graph neural network models for the automated generation of locking techniques; and 3) implementing the proposed design schemes in hardware, spanning both legacy and mixed modes. Collectively, this project will lead to a new design paradigm and novel infrastructure supported by graph neural networks, aiming to advance research in logic locking.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.