Error Tolerant Machine Learning Systems: Off-Line Test and Tuning and On-Line Correction

Rapid advances in machine learning are driving the design of hardware to support the increased capabilities of modern machines with human-like intelligence. However, this comes with greatly increased complexity of hardware and a large carbon footprint for artificial intelligence (AI) applications such as for natural language processing. This has fueled design trends towards the use of low supply voltages, novel aggressively scaled devices and mixed analog-digital signal processing.

The mix of these trends has made the underlying AI hardware vulnerable to operational uncertainties stemming from manufacturing imperfections and noise-induced transient errors. Such uncertainties can cause malfunction of AI driven applications with catastrophic consequences for safety-critical systems such as for transportation and robotics. Consequently, the goal of this project is to develop fundamental algorithms and infrastructure that allow error-resilient operation of AI systems under the above threats across diverse operating conditions, without significant impact on system cost and complexity.

This will advance the delivery of highly dependable AI driven systems, so essential for rapid societal adoption of AI as well as for national defense. The project will support inclusive education of graduate and undergraduate students, development of educational and experimental infrastructure, and technology transfer to industry.

To address the uncertainties above, the research team aims to develop methods for efficient post-manufacture testing and tuning of deep neural networks (DNNs) with energy-efficient analog crossbar arrays that have been shown in prior research to be vulnerable to manufacturing process variations, resulting in significant drop in DNN performance. The underlying test methods that target manufacturing variability will also be very effective in detecting hard defects such as electrical shorts and opens.

Testing and post-manufacture tuning algorithms that offer significant yield improvement over the state of the art will be developed, with tuning times of the order of seconds as opposed to hours for current techniques, reducing device manufacturing and test cost. In parallel, algorithms for on-line error detection, diagnosis and correction of radiation and noise-induced transient soft errors in digital and analog accelerators for novel Artificial Intelligence computing paradigms will also be developed.

The goal is to develop scalable error resilience frameworks for a wide range of learning abstractions including recurrent neural networks, transformers, reinforcement learning algorithms and spiking networks. The key objective is to achieve detection and correction of errors with near-zero latency and minimal computational overhead without extensive retraining of the neural network or modifications to accelerator hardware.

This project is co-funded by the Software and Hardware Foundations (SHF) and Discovery Research PreK-12 (DRK12) programs. DRK12 is an applied research program that supports STEM education PreK-12.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.